1. Field of the Invention
The present invention relates to a semiconductor device having multilayer electrode structure.
2. Description of the Prior Art
FIG. 1A is a plan view showing a conventional power transistor, and FIG. 1B is a sectional view taken along the line C1--C1 in FIG. 1A. As shown in these figures, an N.sup.- -type collector layer 2 is formed on an N.sup.+ -type collector layer 1. A P-type well region 3 is formed on an upper layer part of the N.sup.- -type collector layer 2 by diffusing a P-type impurity. A plurality of N.sup.+ -type emitter regions 4 are partially formed on the surface of the P-type well region 3 by selectively diffusing an N-type impurity of high concentration. Oxide films 5 are selectively formed over the P-type well region 3 and parts of the N-type collector layer 2 provided with no P-type well region 3 as well as regions over the P-type well region 3 and the N.sup.+ -type emitter regions 4. FIG. 1A shows no such oxide films 5, in order to avoid complicatedness of the plan view. A base electrode 16 is formed on the P-type well region 3 while an emitter electrode 17 is formed on the N.sup.+ -type emitter regions 4 to be insulated from each other.
In the power transistor having such structure, the emitter electrode 17 is formed on the N.sup.+ -type emitter regions 4 in a finger-like manner, and hence distribution of current flowing in the emitter electrode 17 is inuniformalized due to longitudinal positional differences between the N.sup.+ -type emitter regions 4, to hinder supply of large current. Further, refinement of the emitter electrode 17 is extremely limited due to etching work accuracy in formation of the electrodes since the base electrode 16 must be provided between the N.sup.+ -type emitter regions 4, to hinder high-speed operation at turn-off time etc.
Thus, it has been difficult to realize the supply of large current and high-speed operation without damaging the degree of integration in the structure of the power transistor shown in FIGS. 1A and 1B.
In order to solve the aforementioned problems, there has been proposed a power transistor having two-layer electrode structure, as shown in FIGS. 2A and 2B. FIG. 2A is a plan view showing such a power transistor having two-layer electrode structure, and FIG. 2B is a sectional view taken along the line C2--C2 in FIG. 2A.
As shown in these figures, an interlayer isolation film 9 is formed to entirely cover the upper surface of a base electrode 16 which is formed between portions of an emitter electrode 17 except for a part 16' of the base electrode 16. An emitter electrode 27 is formed on a tetragonal region including all N.sup.+ -type emitter regions 4. This emitter electrode 27 is in contact with the entire emitter electrode 17 which is provided under the same, while being entirely insulated from a base region 3, which is provided under the emitter electrode 27, through the interlayer isolation film 9. A base electrode 26 is further formed on the part 16' of the base electrode 16 provided with no interlayer isolation film 9. The electrodes are thus provided in two layer (16 and 17; 25 and 27) to increase the formation area of the emitter electrode 27 without deteriorating the degree of integration, thereby enabling supply of large current and high speed operation.
Thus, the semiconductor device of multilayer electrode structure has been generally employed in order to increase the formation areas of the electrodes without deteriorating the degree of integration.
In the conventional multilayer electrode structure, however, the second-layer electrodes 26 and 27 must necessarily be formed on the first-layer electrodes 16 and 17. In general, such electrodes are formed of aluminum. For example, it is necessary to selectively form the interlayer insulation film 9 after formation of the first-layer electrodes 16 and 17 in the power transistor shown in FIGS. 2A and 2B, while there is a strong probability that oxide films are formed on the surfaces of the electrodes 16 and 17 in formation of the interlayer isolation film 9. When the electrodes 26 and 27 are formed on the surfaces of the electrodes 16 and 17 being in such states, electrical barriers are inevitably defined between the pairs of electrodes 16 and 26 as well as 17 and 27.
In order to form a second-layer electrode on a first-layer electrode, therefore, it is necessary to clean the surface of the first-layer electrode before forming the second-layer electrode. Thus, the second-layer electrode is preferably formed by a sputtering process, not by a generally employed vapor deposition process. This is because the surface of the first-layer electrode is cleaned by sputter etching in the sputtering process in advance of accumulation of an aluminum film for forming the second-layer electrode.
However, although the sputtering process is excellent in fabrication of an aluminum film of about 1 .mu.m in thickness, it requires excessive time and cost in order to form a relatively thick aluminum film of 4 to 10 .mu.m in thickness for a power transistor. This is because the sputtering process is higher in apparatus cost and slower in aluminum accumulation rate as compared with the vacuum deposition process.